CY7C1372B, CY7C1370B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM

Cypress Semiconductor

The CY7C1372B by Cypress Semiconductor is a (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM. Below is the official datasheet preview.

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CY7C1372B (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM by Cypress Semiconductor - Datasheet Preview — Official preview page of the **CY7C1372B** (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM datasheet (Cypress Semiconductor).

Datasheet Details

Part number	CY7C1372B, CY7C1370B
Manufacturer	Cypress Semiconductor
File Size	811.36 KB
Description	(CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
Datasheet	CY7C1370B_CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C1372B, CY7C1370B. Please refer to the document for exact specifications by model.
Additional preview pages of the CY7C1372B datasheet.

CY7C1372B Product details

Description

The CY7C1370B and CY7C1372B SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa.

Features

Zero Bus Latency, no dead cycles between Write and Read cycles.
Fast clock speed: 200, 167, 150, and 133 MHz.
Fast access time: 3.0, 3.4, 3.8, and 4.2 ns.
Internally synchronized registered outputs eliminate the need to control OE.
Single 3.3V.
5% and +10% power supply VDD.
Separate VDDQ for 3.3V or 2.5V I/O.
Single WE (Read/Write) control pin.
Positive clock-edge triggered address, data, and control signal register.

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Published: Jan 25, 2010 |