CY7C1372B Datasheet | Cypress

CY7C1370B CY7C1372B 512K × 36/1M × 18 Pipelined SRAM with No BL Architecture Features - Zero Bus Latency, no dead cycles between Write and Read cycles - Fast clock speed: 200, 167, 150, and 133 MHz - Fast access time: 3.0, 3.4, 3.8, and 4.2 ns - Internally synchronized registered outputs eliminate the need to control OE - Single 3.3V - 5% and +10% power supply VDD - Separate VDDQ for 3.3V or 2.5V I/O - Single WE (Read/Write) control pin - Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications - Interleaved or linear four-word burst capability - Individual byte Write (BWSa- BWSd) control (may be tied LOW) - CEN pin to enable clock and suspend operations - Three chip enables for simple depth expansion - JTAG boundary scan (BGA package only) - Available in 119-ball bump BGA and 100-pin TQFP packages - Automatic power down available using ZZ mode or CE deselect inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE1, CE2, and CE3), cycle start input (ADV/LD), Clock enable (CEN), byte Write Enables (BWSa, BWSb, BWSc, and BWSd), and Read-Write Control (WE). BWSc and BWSd apply to CY7C1370B only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either Read or Write. A Clock enable (CEN) pin allows operation of the CY7C1370B/CY7C1372B to be suspended as long as necessary. All synchronous inputs are ignored when CEN is HIGH and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE3) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (Read or Write) will be pleted. The data bus will be in high-impedance state two cycles after the chip is deselected or a Write cycle is initiated....